Designing with Uncertainty - Opportunities & Challenges
Download the Final Programme 
The Designing with Uncertainty - Opportunities & Challenges workshop will be held in the historic city of York. The workshop aims to highlight and discuss emerging trends and future directions in the field of device and circuit design, and will feature invited position papers from world-leading researchers and industrialists across the field.
The technical programme will focus upon the potential for future developments within the field of device and circuit design, addressing areas such as:
- Variability modelling, prediction fabrication and solutions
- Predicting future technologies
- Performance Improvement through Reconfiguration
- Designing with unreliable components
- Fault-tolerant design, recovery through reconfiguration
- Electronic design optimisation
- Design for test, built-in self test
- New and emerging devices (biological, carbon, etc)
- Innovative design techniques (e.g. bio-inspired)
Extended versions of the best submissions will be considered for a Special Issue of the IET journal on Computer & Digital Techniques after a further refereeing process. Click here to view the call for papers.
Attending the Workshop
We welcome attendees from all areas of the device and circuit design community. Thanks to funding from the EPSRC, registration is free for a limited number of places. We also have a number of student bursaries available, which will contribute towards the travel and accommodation costs of registered students who are presenting at the workshop. If you would like to attend, please see the
registration page.
Getting to the Workshop
The workshop is being held in the Law & Management Building, located on the University of York's new Heslington East campus.
To reach Heslington East by public transport, take bus lines 44 or 4, both of which run between the railway station and the University, and get off at the last stop. See here for locations of intermediate bus stops. The journey takes approximately 15-20 minutes.
View larger map
The following speakers will be giving invited talks at the workshop.
Peter Cheung —
On-silicon Instrumentation - An Approach to Alleviate the Variability Problem
Abstract
As feature sizes of VLSI circuits continue to shrink, manufacturing process variation and device ageing are resulting in increasing delay variability and lower reliability. The assumption that all chips are identical will result in the need of employing large design margins to accommodate worst-case delays. This significantly erodes the gains obtained through technology scaling. Configurable technology such as Field Programmable Gate Arrays offers a new approach to future digital VLSI designs, which may alleviate this problem. By incorporating on-chip delay measurement techniques to characterize and monitor devices, it may be possible to alleviate some of the issues caused by increased variability and accelerated ageing.
In this talk, the potential of combining on-chip measurement techniques with the power of reconfigurability will be exposed and demonstrated.
Peter Cheung is a Professor of Digital Systems and Head of the Department of Electrical & Electronic Engineering at Imperial College, UK.
Asen Asenov —
Device-Technology Co-Optimisation (DTCO) in the Presence of Acute Variability
Abstract
Device-Technology Co-Optimisation is key for success in advanced technology nodes. For few technology generations already this has been essential element of SRAM cell technology co-development and co-design but the extension of this approach to other digital and analogue circuit elements is critical for delivering best performance and power and for gaining competitive advantage in the market place. The role of DTCO increases in the migration to novel technology solution like FinFETs and FDSOI MOSFETs. Simultaneously acute process and statistical variability affects the design in contemporary and future CMOS technologies. The integration of accurate variability models and simulations techniques is imperative in the DTCO process.
In this paper we present the GSS technology to circuit simulation tool chain and flow that efficiently and accurately supports DTCO from the TCAD stage, trough compact models to process variability aware statistical circuit simulation. We will provide comprehensive examples how this flow can be used for co-optimization of FinFET technology and SRAM design at 16/14 nm CMOS technology generation and beyond. We will also emphasise on the predictive capabilities of the tool chain responding to the growing needs of the large fabless community to optimise core circuits in their design as early as possible.
Asen Asenov is a fellow of the Royal Academy of Scotland, a Senior Member of IEEE and a member of the IEEE EDS TCAD Committee, as well as co-founder, CEO and director of Gold Standard Simulations (GSS) Ltd.
(read more)
Asen Asenov (FIEEE, FRSE) received a MSc degree in solid state physics from Sofia University, Bulgaria in 1979 and a PhD degree in physics from The Bulgarian Academy of Science in 1989.
He has ten years of industrial experience as a head of the Process and Device Modelling Group in the Institute of Microelectronics, Sofia, leading in 1986 the development of one of the first integrated process and device CMOS simulators IMPEDANCE. In 1989–1991 he was a Visiting Professor at the Physics Department of The Technical University of Munich, Germany. He joined the Department of Electronics and Electrical Engineering at the University of Glasgow in 1991, and served as a Head of Department in 1999-2003.
As a James Watt Professor in Electrical Engineering and the Leader of the Glasgow Device Modelling Group Asenov directs the development of 2D and 3D quantum mechanical, Monte Carlo and classical device simulators and their application in the design of advanced and novel CMOS devices. He has pioneered the simulations of statistical variability in nano-CMOS devices including random dopants, interface roughness, line edge roughness and gate stack granularity. He has over 660 publications and more than 170 invited talks in the above areas (see here).
Professor Asenov is also a co-founder, CEO and a director of Gold Standard Simulations (GSS) Ltd. (http://www.goldstandardsimulations.com).
Professor Asenov is a fellow of the Royal Academy of Scotland, an IEEE Fellow, a member of the IEEE Electron Device Society Technology Computer-Aided Design Committee and of the BP Fellowship Committee. He is co-author of European Nanoelectronics Advisory Council (ENIAC) Strategic Research Agenda (SRA) and the 2011 edition of the ITRS. He acted on behave of EC as and reviewer of more than 15 EC projects and as an evaluator of several FP5, FP6 and FP7 calls. He has been a general chair, co-chair and TPC chair for many international conferences and workshops.
Abstract
CPU microarchitecture development begins several years before initial product design using that microarchitecture, and so requires information about SoC manufacturing processes significantly before it is released by the foundries. Close collaboration with the foundries, known as “Design-Technology Co-Optimization”, or DTCO, allows the mutual influence of microarchitecture, physical IP (standard cells and memories), and process technology. An important aspect of DTCO from the CPU development side is the availability of predictive technology, which allows design exploration in the form of trial runs of synthesis, place and route to determine the predicted effects of various technology choices on CPU power, performance, and area.
This talk provides some background on ARM efforts in DTCO and shows how predictive technology can be used to investigate microarchitectural design space.
Robert C. Aitken is an ARM Fellow and heads ARM’s R&D efforts in advanced silicon technology. He is also an IEEE Fellow and holds a PhD degree from McGill University in Canada.
Abstract
FPGAs are programmed after manufacture to customize the chip to the application being performed. This customization step can also be used to deal with manufacturing variation. This presentation describes methods to use FPGA programming to deal with random performance variation, yield loss and even premature aging.
Steve Trimberger is a Xilinx Fellow, currently heading the Circuits and Architectures Group in Xilinx Research Labs in San Jose, California. He has been working with Xilinx since 1998 and was the technical leader for many aspects of the XC4000 design.
Abstract
There is continuing and significant academic research efforts to improve the reliability of embedded systems in the presence of hardware faults and process variation. The presentation will review some of the highlights of this research and also report on some effective industrial practices in reliable hardware design. The aim is to motivate focused research in system-level design and automation tools for future reliable and energy-efficient embedded systems using many-core processors.
Bashir M. Al-Hashimi holds the endowment ARM chair in Computer Engineering, Electronics and Computer Science (ECS), University of Southampton.
(read more)
He is the director of the Pervasive Systems Centre, and co-director of the ARM-ECS research centre. He is the project leader for the £5.6 million EPSRC Programme PRiME: Power-efficient, Reliable, Many-core Embedded systems. In 2013 he was elected Fellow of the Royal Academy of Engineering, and in 2009, he was elected fellow of the IEEE. He has published 300 papers, authored or co-authored 5 books, and graduated 32 PhD students. He served as Technical Programme chair and General Chair of DATE conference in 2009 and 2011, respectively.
Roger Woods —
FPGA-based Realizations of Embedded Systems
Abstract
Various silicon platforms are emerging for realizing complex signal and data processing systems. Technologies such as Graphical Processing Units (GPUs) and FPGAs offer different processing profiles in terms of speed and power but also present different challenges in terms of programming.
This presentation will consider create of high performance designs particularly using FPGAs, and how to reduce programming times effectively. In particular, the talk will consider the realization of a FPGA-based programmable solutions for image processing and efforts in creating a programming flow to program them.
Roger Woods holds a chair in the School of Electronics, Electrical Engineering and Computer Science at Queen’s University Belfast and is also Chief Technology Officer of Analytics Engines Ltd, a company which creates accelerators to enhance the speed and efficiency of software applications.
Sani Nassif —
Medical Treatment For Variability: Lessons from Circuits Applied to Cancer Radiation Therapy
Abstract
The Hippocratic Oath reads (in part) "I will prescribe regimens for the good of my patients according to my ability and my judgment and never do harm to anyone". This is in rather start difference to engineering, where one might happily build a model of some object for the sole purpose of destroying it in -for example- a reliability test. This puts Doctors at somewhat of a disadvantage to Engineers when it comes to doing experimental research! In radiation therapy in particular, there are a number of sources of variability which significantly impact treatment outcome. Modeling and analyzing these variability sources turns out to be quite similar to doing the same for circuits.
This talk will expand on these ideas and show how ideas from engineering can be nicely applied to this quite different topic area.
Dr. Nassif is the president elect of the IEEE Council on EDA (CEDA). He is an IEEE Fellow, a member of the IBM Academy of Technology, a member of the ACM and the AAAS.
Abstract
In conventional electronic integrated circuit architectures, information is processed through a network of simple logic gates which act on Boolean inputs to generate the appropriate Boolean output. Similar Boolean logic gates have today been realised using biomolecular components where information is encoded within the nucleotide sequence of DNA or in the amino acid sequence of proteins and peptides. Unlike electronic logic in which information is processed sequentially, biomolecular logic gates use the combinatorial assembly of biological sequences to test large numbers of solutions in parallel. However, many biomolecular logic gates use incompatible input and output signals limiting the integration of multiple biomolecular logic gates into complex integrated circuits.
This talk will present recent progress towards a hybrid biomolecular electronics, assembled from bio-functionalised electronic circuitry that combines the large-scale integration inherent to conventional electronics with the parallelism of biomolecular logic.
Steve Johnson is a lecturer at the Department of Electronics in the University of York, with research focusing of Biomolecular Electronics.
Martin Trefzer —
Sense, Adapt, Survive: An Evolutionary Hardware Perspective
Abstract
Increasing integration density, performance and power efficiency of electronic systems has been achieved in the past simply through shrinking device sizes. As atomistic scales are now reached, stochastic variations become prevalent making components noisy and unreliable, which makes reliable design impossible. In this respect, technological systems are far behind biological organisms which have long since accomplished the feat of not only operating reliably with highly variable components, but also maintaining and tuning themselves in changing environments, when faults occur or they are otherwise perturbed. Biological mechanisms enabling this have co-evolved with the organisms, hence, are perfectly adapted to the requirements of their embodiment. In this context, evolutionary hardware is about hardware that offers the capability to change its structure and behaviour in order to automatically optimise its operation for a specific task or environment, taking inspiration from biological organisms with natural evolution as Nature’s guiding optimisation principle.
Martin Trefzer is a lecturer at the Department of Electronics in the University of York, with research focusing on adaptive hardware and evolutionary computation.
Law & Management Building,
University of York
The workshop will be held in the Law & Management Building, located at the University of York's newly developed Heslington East campus.
Click here for directions.
York
The University of York is situated in one the most beautiful cities in Europe (voted European Tourism City of the Year in 2007). Midway between the capital cities of London and Edinburgh, and with excellent transport links, the city has a 2000 year history, yet a modern outlook.
The city (then named Eboracum) was founded by the Romans. It has always been an important centre: it was one of the capitals of Roman Britain, and for a short period the entire Roman Empire was governed from York. In the ninth century CE, the city (then called Jorvik) was made the capital of most of northern England by the Vikings, and remainded so for most of the next eight hundred years.
Largely untouched by the industrial revolution, the centre of York today retains many period buildings, cobbled streets and pedestrian-only areas, lined with cafes and speciality shops. Tourism is now a major industry, and York is the second most-visited city in England (after London).
Travelling by Air
Manchester Airport is a large airport in the north of England, and has a wide range of international flights and connections via London. Trains run directly to York from the airport station and take just under 2 hours (
see timetable). This is generally the most convenient option.
London Heathrow is the largest UK airport, with flights to a wide range of international destinations. Upon arrival, take the Heathrow Express train to Paddington station, then change to the Hammersmith and City underground line to reach King's Cross station (this takes about 30-45 minutes). Direct trains run frequently to York and take about 2 hours. London Gatwick, London Stansted and London Luton also have public transport connections to York.
Leeds-Bradford is the closest airport to York, and has some international flights. Taxis to York take around 45 minutes. Other nearby airports with public transport connections include Newcastle, Durham Tees Valley and Humberside.
Travelling by Rail
From Europe — York can be reached in around 5 hours from Paris or Brussels by train, by taking the Eurostar from Paris Nord to London St Pancras, with a short transfer (5 minute walk) to London Kings Cross for a direct rail service to York.
From the United Kingdom — York is on the East Coast main line from London to Edinburgh, just over two hours away from London King's Cross and around 2.5 hours from Edinburgh. There are also direct express services to many other major cities, including Manchester, Newcastle, Sheffield, Leeds, Birmingham and Glasgow.
Click here for directions to the venue.
Want to meet up on Sunday night?
Sunday 16th March - Black Swan Meetup
This event will be held at one of the UK's most popular museums, the National Railway Museum. Dinner will be served in the great hall, amongst some of the world's most iconic locomotives.